A thin film transistor-liquid crystal display (TFT-LCD) is composed of pixel matrices defined by intersecting gate lines and data lines in both a horizontal direction and a vertical direction. When the TFT-LCD performs display, a gate line of each row is supplied with a gate signal to switch on the TFT controlled by the gate line of each row, such that a pixel electrode positioned in the same pixel as the TFT is connected with a date line. Then a voltage of a display signal is inputted to the pixel electrode by inputting the display signal into the data line. By controlling liquid crystal molecules at a position corresponding to the pixel electrode to deflect, different transmittances can be obtained and accordingly control over the grey level or color of a displayed image can be achieved. However, in the case of a high resolution, there are many outputs for both the gate driving and the source driving of the display, and the length of the driving circuit path will also increase, which will be adverse to the bonding process of a modular driving circuit.
To address the above concerns, a gate driver on array (GOA) circuit design is often used in the manufacture of an existing display, wherein a thin film transistor (TFT) gate switching circuit is integrated on an array substrate of a display panel to form scan driving of the display panel, which can save the bonding region and the peripheral wiring space of the gate driving circuit, thereby achieving an aesthetic design of the display panel with a side symmetry and a narrow bezel.
In the prior art, in order to achieve progressive scan, the GOA circuit comprises a plurality of shift register units. As shown in FIG. 1, a shift register unit in a traditional low temperature poly-silicon (LTPS) GOA circuit may constitute two latches (a first latch 01 and a second latch 02). Each latch 01 may comprise an inverter, two transmission gates and a NAND gate, and is capable of transmitting and shifting an inputted control signal D by using a clock signal Clk (or Clk_). Specifically, upon switching on of the first latch 01, the control signal D inputted by a preceding stage shift register unit enters the latch 01, at which point the second latch 02 is switched off such that the signal cannot be inputted. When the next clock signal arrives, the first latch 01 is switched off to latch the control signal D, at which point the second latch 02 is switched on to allow the control signal D to enter the second latch 02 and be outputted therefrom, thereby achieving the shifting operation of the control signal D.
Within the scan time for a frame, the shift register unit will be in a non-operational state when it accomplishes shifting output. Therefore, for the entire display panel, when a stage of shift register unit is in an operational state, all other shift register units are in a non-operational state. However, even in a non-operational state, the transmission gates controlled by the clock signal in each shift register unit will still be switched on and off frequently by the clock signal during signal flips. As a transmission gate is formed by complementary transistors connected in parallel, a gate capacitor composed of a gate and a substrate in the transistor will be charged and discharged many times during the switching on and off of the transmission gates. As such, the clock signal loaded onto the transmission gates will cause much useless power consumption, which greatly reduces the utilization efficiency of the display driving capacity.